1. Field of the Invention
The present invention relates to a semiconductor device and a method of making the device, and in particular, to a semiconductor device in which adjacent elements thereof are isolated from each other and a method of making the device.
2. Description of the Related Art
Heretofore, there has been known a semiconductor device in which adjacent elements thereof are isolated from each other by an element isolation region. As such an isolation region, there has been used a transistor (gate) region provided between the adjacent elements as described in U.S. Pat. No. 4,570,331 issued to S. S. Eaton Jr. et al. and in "Fully Planarized 0.5 .mu.m Technologies for 16M DRAM" by W. Wakamiya et al. in IEDM Tech. Dig. (1988), p.p. 246-249. To manufacture an element isolation transistor (gate) of this kind, ions of boron B.sup.+ 102 are first implanted into the overall surface of a p-type silicon substrate 101 to form an impurity diffusion region 103 as shown in FIG. 2A. Next, there are sequentially fabricated a first silicon dioxide layer 104, a polycrystalline silicon layer 105, and a second silicon dioxide layer 106 as shown in FIG. 2B. Subsequently, the layers 104 to 106 are patterned by etching process to form an element isolating three-layer structure 112 including an element isolation gate layer 107, an element isolation gate electrode 108, and an element isolation gate silicon dioxide layer 109, as shown in FIG. 2C. In addition, on a side wall of the three-layer structure 112, there is formed a side wall oxide layer 110 for element isolation. Thereafter, on the element isolation gate electrode 108, there is made a contact terminal (not shown), through which a potential can be applied to the gate electrode. Thus, the process of manufacturing the element isolation region is completed. After the element isolation region is thus formed to provide an isolated element forming region 111, an element such as a transistor is formed in the region 111.
The impurity diffusion region 103 is disposed to increase the threshold voltage of a parasitic transistor, which is formed of a wiring layer (not shown) formed on the element isolation gate region 112 serving as a gate region and surface regions of the substrate on both sides of the three-layer structure 112 respectively functioning as a source region and a drain region, so that a high performance of element isolating ability of the isolation region can be obtained. Boron ions B.sup.+ 102 are injected in the region 103 at a dose of about 1.times.10.sup.12 atoms/cm.sup.2 with an injection energy of 10-50 KeV.
However, boron ions (B.sup.+) are injected in the overall surface of the silicon substrate 101 for a higher isolation performance of the isolation regions. Moreover, in a subsequent process, boron ions (B.sup.+) are implanted into the element forming region 111 to fabricate therein an element such as a transistor. Consequently, in the resultant semiconductor device there is a low stability of elements formed in the regions 111.
In "A 0.5 .mu.m Isolation Technology Using Advanced Poly Silicon Pad LOCOS (APPL)" by T. Nishihara et al, IEDM 1988, pp 100 to 103, it is also proposed to increase the element isolation ability by channel stop implantation and deep channel implantation.